1. Field of the Invention
The present invention relates generally to a stacked-gate nonvolatile semiconductor memory cell in which a floating gate electrode and a control gate electrode are stacked, and a method of manufacturing the same. In particular, the invention relates to a nonvolatile semiconductor memory cell, which is effectively applicable to a case where an inter-electrode insulation film lying between a floating gate electrode and a control gate electrode has a substantially flat structure, and to a method of manufacturing the same.
2. Description of the Related Art
In the prior art, a stacked-gate memory cell, which has a stacked-gate structure wherein a floating gate electrode and a control gate electrode are stacked, has widely been used as an electrically programmable nonvolatile semiconductor memory cell. In order to increase a cell coupling ratio in this memory cell, a method has been proposed wherein the stacked-gate structure is formed in an inverse-taper shape.
FIG. 7A and FIG. 7B illustrate this type of memory cell structure. FIG. 7A is a cross-sectional view taken in a channel length direction, and FIG. 7B is a cross-sectional view taken in a channel width direction. In the Figures, reference numeral 201 denotes a silicon substrate, numeral 202 a tunnel insulation film, numeral 203 a floating gate electrode formed of a polysilicon layer, numeral 204 a buried insulation film for device isolation, numeral 205 an inter-electrode insulation film, numeral 206 a control gate electrode formed of a polysilicon layer, and numeral 207 source/drain diffusion layers. The stacked-gate structure is formed in an inverse-taper shape, and the source/drain diffusion layers 207 are formed using an oblique ion implantation method with an incidence angle of 5°.
In the above-described structure, an area of the floating gate electrode 203, which contacts the inter-electrode insulation film 205 is greater than an area of the floating gate electrode 203, which contacts the tunnel insulation film 202. Thus, the cell coupling ratio increases. Accordingly, the write/erase operation voltage can be decreased.
However, this type of memory cell has the following problems. The width of the substrate-side part of the floating gate electrode is less than a normal width of the cell, and the oblique ion implantation is used. As a result, the channel width of the cell transistor becomes much less than the cell width. If the cell size is reduced, the short channel effect becomes conspicuous and it becomes difficult to control the threshold voltage value. Furthermore, if a vertical ion implantation method is substituted for the oblique ion implantation method in forming the source/drain diffusion layers 207 in order to suppress the short channel effect, the shapes of finished diffusion layers 207 would vary from cell to cell. In this case, too, it becomes difficult to control the threshold voltage value.
In the cell structure shown in FIGS. 7A and 7B, the stacked-gate structure has an inverse-taper shape. As a result, a so-called “void” occurs when the insulation film 204 is buried between cells. It is difficult to completely bury the insulation film 204 between cells. Consequently, the reliability of cells deteriorates.
As has been described above, in the conventional stacked-gate nonvolatile semiconductor memory cell, if the stacked-gate structure is formed in the inverse-taper shape in order to increase the cell coupling ratio, the control of the threshold voltage becomes difficult due to the short channel effect, and this may lead to a data write malfunction.